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(R)
ISL6597
Data Sheet November 22, 2006 FN9165.0
Dual Synchronous Rectified MOSFET Drivers
The ISL6597 integrates two ISL6596 drivers and is optimized to drive two independent power channels in a synchronous-rectified buck converter topology. These drivers, combined with an Intersil multiphase PWM controller, form a complete high efficiency voltage regulator solution. The IC is biased by a single low voltage supply (5V), minimizing driver switching losses in high MOSFET gate capacitance and high switching frequency applications. Each driver is capable of driving a 3nF load with less than 10ns rise/fall time. Bootstrapping of the upper gate driver is implemented via an internal low forward drop diode, reducing implementation cost, complexity, and allowing the use of higher performance, cost effective N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously. The ISL6597 features 4A typical sink current for the lower gate driver, enhancing the lower MOSFET gate hold-down capability during PHASE node rising edge, preventing power loss caused by the self turn-on of the lower MOSFET due to the high dV/dt of the switching node. The ISL6597 also features an input that recognizes a highimpedance state, working together with Intersil multi-phase 3.3V or 5V PWM controllers to prevent negative transients on the controlled output voltage when operation is suspended. This feature eliminates the need for the schottky diode that may be utilized in a power system to protect the load from negative output voltage damage.
Features
* 5V Quad N-Channel MOSFET Drives for Two Synchronous Rectified Bridges * Adaptive Shoot-Through Protection * Programmable Deadtime for Efficiency Optimization * Diode Emulation for Efficiency and Pre-Biased Startup * 0.4 On-Resistance and 4A Sink Current Capability * Supports High Switching Frequency - Fast Output Rise and Fall - Ultra Low Tri-State Hold-Off Time (20ns) * Low VF Internal Bootstrap Diode * Low Bias Supply Current * Support 3.3V and 5V PWM Input * Enable Input and Power-On Reset * QFN Package - Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat No Leads-Product Outline - Near Chip-Scale Package Footprint; Improves PCB Utilization and Thinner in Profile * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Core Voltage Supplies for Intel(R) and AMD(R) Microprocessors * High Frequency Low Profile High Efficiency DC/DC Converters * High Current Low Voltage DC/DC Converters * Synchronous Rectification for Isolated Power Supplies
Ordering Information
PART NUMBER (Note) ISL6597CRZ PART MARKING 65 97CRZ TEMP. RANGE (C) PACKAGE (Pb-Free) PKG. DWG. #
Related Literature
* Technical Brief TB389 "PCB Land Pattern Design and Surface Mount Guidelines for QFN (MLFP) Packages" * Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)
0 to +70 16 Ld 4x4 QFN L16.4x4
Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved AMD(R) is a registered trademark of Advanced Micro Devices, Inc. All other trademarks mentioned are the property of their respective owners.
ISL6597 Pinout
ISL6597 (16 LD QFN) TOP VIEW
PHASE1 13 12 UGATE1 17 PGND PVCC 3 EN 4 5 PGND 6 LGATE2 7 VCTRL 8 PHASE2 10 BOOT2 9 UGATE2 11 BOOT1 PWM2 PWM1 15
16 GND 1 LGATE1 2
Block Diagram
ISL6597
VCC PVCC VCTRL BOOT1 UGATE1
VCC 14
3.5K PWM1 3.5K
SHOOTTHROUGH PROTECTION
PHASE1
CHANNEL 1
PVCC1
LGATE1 PGND
EN VCTRL
CONTROL LOGIC
PGND BOOT2 UGATE2
PVCC
3.5K PWM2 3.5K GND SHOOTTHROUGH PROTECTION
PHASE2 PVCC
CHANNEL 2
LGATE2 PGND PAD
2
FN9165.0 November 22, 2006
ISL6597 Typical Application - Multiphase Converter Using ISL6597 Gate Drivers
+3.3V
BOOT1
+12V
UGATE1 VCTRL PHASE1 +5V +3.3V PVCC VCC FB VSEN COMP VCC ISEN1 PGOOD EN PWM1 PWM2 MAIN ISEN2 CONTROL ISL65xx PWM1 PWM2 LGATE2 PHASE2 EN UGATE2 DUAL DRIVER ISL6597 BOOT2 +12V LGATE1
VID
GND
PGND
+VCORE ISEN3 FS/DIS PWM3 PWM4 GND ISEN4 UGATE1 VCTRL PHASE1 +5V LGATE1 PVCC VCC DUAL DRIVER ISL6597 BOOT2 EN UGATE2 PWM1 PWM2 LGATE2 PHASE2 +12V +3.3V
BOOT1
+12V
GND
PGND
3
FN9165.0 November 22, 2006
ISL6597
Absolute Maximum Ratings
Supply Voltage (PVCC, VCC) . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Input Voltage (VEN, VPWM) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V BOOT Voltage (VBOOT-GND). . . -0.3V to 25V (DC) or 36V (<200ns) BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . -0.3V to 7V (DC) -0.3V to 9V (<10ns) PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V (DC) GND -8V (<20ns Pulse Width, 10J) to 30V (<100ns) UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT VPHASE - 5V (<20ns Pulse Width, 10J) to VBOOT LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V GND - 2.5V (<20ns Pulse Width, 5J) to VCC + 0.3V Ambient Temperature Range . . . . . . . . . . . . . . . . . .-40C to +125C HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Thermal Information
Thermal Resistance (Notes 1 and 2) JA(C/W) JC(C/W) QFN Package . . . . . . . . . . . . . . . . . . 46 8.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0C to +70C Maximum Operating Junction Temperature. . . . . . . . . . . . . +125C Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10%
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. +150C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Constantly operated at 150C may shorten the life of the part.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. 2. JC, "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER VCC SUPPLY CURRENT Bias Supply Current
These specifications apply for TA = 0C to +70C, unless otherwise noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IVCC+PVCC
PWM pin floating, VVCC = VPVCC = 5V FPWM = 300kHz, VVCC = VPVCC = 5V
2.6 -
350 1.7 3.4 3.0 400
4.2 -
A mA V V mV
POR Rising POR Falling Hysteresis BOOTSTRAP DIODE Forward Voltage VCTRL INPUT Turn-On Threshold Hysteresis ENABLE INPUT EN LOW Threshold EN HIGH Threshold EN Hysteresis PWM INPUT Sinking Impedance Source Impedance Tri-State Lower Threshold RPWM_SNK RPWM_SRC VVCC = 3.3V (120mV Hysteresis) VVCC = 5V (300mV Hysteresis) Tri-State Upper Threshold VVCC = 3.3V (110mV Hysteresis) VVCC = 5V (300mV Hysteresis) Tri-State Shutdown Holdoff Time SWITCHING TIME (Note 3, See Figure 1) UGATE Rise Time LGATE Rise Time UGATE Fall Time tRU tRL tFU VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load tTSSHD VF Forward bias current = 2mA
0.3
0.6
0.7
V
2.5 -
2.8 100
-
V mV
1.00 1.40 100
1.34 1.60 260
-
V V mV
1.65 3.00 -
3.5 3.5 1.15 1.55 1.85 3.18 80
1.4 1.75 -
k k V V V V ns
-
8.0 8.0 8.0
-
ns ns ns
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ISL6597
Electrical Specifications
PARAMETER LGATE Fall Time UGATE Turn-Off Propagation Delay LGATE Turn-Off Propagation Delay UGATE Turn-On Propagation Delay LGATE Turn-On Propagation Delay Tri-state to UG/LG Rising Propagation Delay OUTPUT (Note 3) Upper Drive Source Resistance Upper Drive Sink Resistance Lower Drive Source Resistance Lower Drive Sink Resistance NOTE: 3. Guaranteed by Characterization. Not 100% tested in production. RUG_SRC RUG_SNK RLG_SRC RLG_SNK 250mA Source Current 250mA Sink Current 250mA Source Current 250mA Sink Current 1.0 1.0 1.0 0.4 2.5 2.5 2.5 1.0 These specifications apply for TA = 0C to +70C, unless otherwise noted (Continued) SYMBOL tFL tPDLU tPDLL tPDHU tPDHL tPTS TEST CONDITIONS VVCC = 5V, 3nF Load VVCC = 5V, Unloaded, VVCC = 5V, Unloaded, VVCC = 5V, Unloaded, VVCC = 5V, Unloaded, VVCC = 5V, Unloaded MIN TYP 4.0 18 25 18 23 30 MAX UNITS ns ns ns ns ns ns
Functional Pin Description
PACKAGE PIN # 1 2 3 4 5 6 7 8 9 10 PIN SYMBOL GND LGATE1 PVCC EN PGND LGATE2 VCTRL PHASE2 UGATE2 BOOT2 FUNCTION Bias and reference ground. All signals are referenced to this node. Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET. This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor from this pin to PGND. Enable input pin. Connect this pin high to enable and low to disable the driver. It is the power ground return of both low gate drivers. Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET. This pin sets the PWM logic threshold. Connect this pin to 3.3V source for 3.3V PWM input and pull it to 5V source for 5V PWM input. Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This pin provides a return path for the upper gate drive. Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET. Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this pin and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value. Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this pin and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value. Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET. Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This pin provides a return path for the upper gate drive. Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic capacitor from this pin to GND. The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during operation, see the tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller. The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during operation, see the tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller. Connect this pad to the power ground plane (PGND) via thermally enhanced connection.
11
BOOT1
12 13 14 15
UGATE1 PHASE1 VCC PWM1
16
PWM2
17
PAD
5
FN9165.0 November 22, 2006
ISL6597 Timing Diagram
2.5V PWM tPDHU tPDLU tRU tPTS 1V UGATE tRU tTSSHD tFU
LGATE 1V tRL tTSSHD tPDLL tPDHL tFL
tPTS
FIGURE 1. TIMING DIAGRAM
Operation and Adaptive Shoot-Through Protection
Designed for high speed switching, the ISL6597 MOSFET driver controls both high-side and low-side N-Channel FETs from one externally provided PWM signal. A rising transition on PWM initiates the turn-off of the lower MOSFET (see Figure 1). After a short propagation delay [tPDLL], the lower gate begins to fall. Typical fall times [tFL] are provided in the Electrical Specifications. Adaptive shootthrough circuitry monitors the LGATE voltage and turns on the upper gate following a short delay time [tPDHU] after the LGATE voltage drops below ~1V. The upper gate drive then begins to rise [tRU] and the upper MOSFET turns on. A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [tPDLU] is encountered before the upper gate begins to fall [tFU]. The adaptive shoot-through circuitry monitors the UGATE-PHASE voltage and turns on the lower MOSFET a short delay time, tPDHL, after the upper MOSFET's gate voltage drops below 1V. The lower gate then rises [tRL], turning on the lower MOSFET. These methods prevent both the lower and upper MOSFETs from conducting simultaneously (shoot-through), while adapting the dead time to the gate charge characteristics of the MOSFETs being used. This driver is optimized for voltage regulators with large step down ratio. The lower MOSFET is usually sized larger compared to the upper MOSFET because the lower MOSFET conducts for a longer time during a switching period. The lower gate driver is therefore sized much larger to meet this application requirement. The 0.4 on-resistance and 4A sink current capability enable the lower gate driver to
absorb the current injected into the lower gate through the drain-to-gate (CGD) capacitor of the lower MOSFET and help prevent shoot through caused by the self turn-on of the lower MOSFET due to high dV/dt of the switching node.
Tri-State PWM Input
A unique feature of the ISL6597 is the programmable PWM logic threshold set by the control pin (VCTRL) voltage. The VCTRL pin should connect to the controller's VCC so that the PWM logic thresholds follow with the VCC voltage level. For applications using single rail 5V to power up both controller and driver, this pin can be tied to the driver VCC, simplifying the trace routing. The ISL6597 also features the adaptable tri-state PWM input. Once the PWM signal enters the shutdown window, either MOSFET previously conducting is turned off. If the PWM signal remains within the shutdown window for longer than the gate turn-off propagation delay of the previously conducting MOSFET, the output drivers are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. The PWM rising and falling thresholds outlined in the Electrical Specifications determine when the lower and upper gates are enabled. During normal operation in a typical application, the PWM rise and fall times through the shutdown window should not exceed either output's turnoff propagation delay plus the MOSFET gate discharge time to ~1V. Abnormally long PWM signal transition times through the shutdown window will simply introduce additional dead time between turn off and turn on of the synchronous bridge's MOSFETs. For optimal performance, no more than 50pF parasitic capacitive load should be present on the
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FN9165.0 November 22, 2006
ISL6597
PWM line of ISL6597 (assuming an Intersil PWM controller is used). allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of +125C. The maximum allowable IC power dissipation for the 16 lead 4x4 QFN packages, with an exposed heat escape pad, is around 2W. See Layout Considerations paragraph for thermal transfer improvement suggestions. When designing the driver into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses due to the gate charge of MOSFETs and the driver's internal circuitry and their corresponding average driver current can be estimated with Equations 2 and 3, respectively,
P Qg_TOT = 2 * ( P Qg_Q1 + P Qg_Q2 ) + I Q * VCC Q G1 * PVCC 2 P Qg_Q1 = -------------------------------------- * F SW * N Q1 V GS1 Q G2 * PVCC 2 P Qg_Q2 = -------------------------------------- * F SW * N Q2 V GS2 Q G1 * N Q1 Q G2 * N Q2 I DR = 2 * ----------------------------- + ----------------------------- * F SW + I Q V GS2 V GS1 (EQ. 2)
Bootstrap Considerations
This driver features an internal bootstrap diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The following equation helps select a proper bootstrap capacitor size:
Q GATE C BOOT_CAP ------------------------------------V BOOT_CAP Q G1 * PVCC Q GATE = ----------------------------------- * N Q1 V GS1
(EQ. 1)
where QG1 is the amount of gate charge per upper MOSFET at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The VBOOT_CAP term is defined as the allowable droop in the rail of the upper gate drive. As an example, suppose two HAT2168 FETs are chosen as the upper MOSFETs. The gate charge, QG, from the data sheet is 12nC at 5V (VGS) gate-source voltage. Then the QGATE is calculated to be 26.4nC at 5.5V PVCC level. We will assume a 100mV droop in drive voltage over the PWM cycle. We find that a bootstrap capacitance of at least 0.264F is required. The next larger standard value capacitance is 0.33F. A good quality ceramic capacitor is recommended.
2.0 1.8 1.6 1.4 CBOOT_CAP (F) 1.2 1.0 0.8 0.6 QGATE = 100nC 0.4 50nC 0.2 20nC 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0 0.0
(EQ. 3)
where the gate charge (QG1 and QG2) is defined at a particular gate to source voltage (VGS1and VGS2) in the corresponding MOSFET datasheet; IQ is the driver's total quiescent current with no load at both drive outputs; NQ1 and NQ2 are number of upper and lower MOSFETs, respectively. The factor 2 is the number of active channels. The IQ VCC product is the quiescent power of the driver without capacitive load and is typically negligible. The total gate drive power losses are dissipated among the resistive components along the transition path. The drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (RG1 and RG2, should be a short to avoid interfering with the operation shoot-through protection circuitry) and the internal gate resistors (RGI1 and RGI2) of MOSFETs. Figures 3 and 4 show the typical upper and lower gate drives turn-on transition path. The power dissipation on the driver can be roughly estimated as:
P DR = 2 * ( P DR_UP + P DR_LOW ) + I Q * VCC R HI1 R LO1 P Qg_Q1 P DR_UP = -------------------------------------- + --------------------------------------- * --------------------R HI1 + R EXT1 R LO1 + R EXT1 2 R HI2 R LO2 P Qg_Q2 P DR_LOW = -------------------------------------- + --------------------------------------- * --------------------2 R HI2 + R EXT2 R LO2 + R EXT2 R GI1 R EXT2 = R G1 + ------------N
Q1
VBOOT (V)
(EQ. 4)
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the switching frequency (FSW), the output drive impedance, the external gate resistance, and the selected MOSFET's internal gate resistance and total gate charge. Calculating the power dissipation in the driver for a desired application is critical to ensure safe operation. Exceeding the maximum 7
R GI2 R EXT2 = R G2 + ------------N
Q2
FN9165.0 November 22, 2006
ISL6597
PVCC BOOT D CGD RHI1 RLO1 G RG1 RGI1 CGS S PHASE Q1 CDS
overcharging, exceeding the device rating. Low-profile MOSFETs, such as Direct FETs and multi-SOURCE leads devices (SO-8, LFPAK, PowerPAK), have low parasitic lead inductances and are preferred.
Layout Considerations
A good layout helps reduce the ringing on the switching node (PHASE) and significantly lower the stress applied to the output drives. The following advice is meant to lead to an optimized layout and performance: * Keep decoupling loops (VCC-GND, PVCC-PGND and BOOT-PHASE) short and wide, at least 25 mils. Avoid using vias on decoupling components other than their ground terminals, which should be on a copper plane with at least two vias. * Minimize trace inductance, especially on low-impedance lines. All power traces (UGATE, PHASE, LGATE, PGND, PVCC, VCC, GND) should be short and wide, at least 25 mils. Try to place power traces on a single layer, otherwise, two vias on interconnection are preferred where possible. For no connection (NC) pins on the QFN part, connect it to the adjacent net (LGATE2/PHASE2) can reduce trace inductance. * Shorten all gate drive loops (UGATE-PHASE and LGATEPGND) and route them closely spaced. * Minimize the inductance of the PHASE node. Ideally, the source of the upper and the drain of the lower MOSFET should be as close as thermally allowable. * Minimize the current loop of the output and input power trains. Short the source connection of the lower MOSFET to ground as close to the transistor pin as feasible. Input capacitors (especially ceramic decoupling) should be placed as close to the drain of upper and source of lower MOSFETs as possible. * Avoid routing relatively high impedance nodes (such as PWM and ENABLE lines) close to high dV/dt UGATE and PHASE nodes. In addition, connecting the thermal pad of the QFN package to the power ground through multiple vias is recommended. This is to improve heat dissipation and allow the part to achieve its full thermal potential.
UGATE
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC D CGD RHI2 RLO2 LGATE G RG2 RGI2 CGS GND S Q2 CDS
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Application Information
MOSFET Selection
The parasitic inductances of the PCB and of the power devices' packaging (both upper and lower MOSFETs) can cause serious ringing, exceeding absolute maximum rating of the devices. The negative ringing at the edges of the PHASE node could increase the bootstrap capacitor voltage through the internal bootstrap diode, and in some cases, it may overstress the upper MOSFET driver. Careful layout, proper selection of MOSFETs and packaging can go a long way toward minimizing such unwanted stress.
PVCC BOOT D
RHI1 RLO1
G Q1 UGATE S PHASE RPH=1-2
Upper MOSFET Self Turn-On Effects At Startup
Should the driver have insufficient bias voltage applied, its outputs are floating. If the input bus is energized at a high dV/dt rate while the driver outputs are floating, due to the self-coupling via the internal CGD of the MOSFET, the UGATE could momentarily rise up to a level greater than the threshold voltage of the MOSFET. This could potentially turn on the upper switch and result in damaging inrush energy. Therefore, if such a situation (when input bus powered up before the bias of the controller and driver is ready) could conceivably be encountered, it is a common practice to place a resistor (RUGPH) across the gate and source of the
FIGURE 5. PHASE RESISTOR TO MINIMIZE SERIOUS NEGATIVE PHASE SPIKE
The D2-PAK, or D-PAK packaged MOSFETs, have large parasitic lead inductances and are not recommended unless a phase resistor (RPH), as shown in Figure 5, is implemented to prevent the bootstrap capacitor from 8
FN9165.0 November 22, 2006
ISL6597
upper MOSFET to suppress the Miller coupling effect. The value of the resistor depends mainly on the input voltage's rate of rise, the CGD/CGS ratio, as well as the gate-source threshold of the upper MOSFET. A higher dV/dt, a lower CDS/CGS ratio, and a lower gate-source threshold upper FET will require a smaller resistor to diminish the effect of the internal capacitive coupling. For most applications, the integrated 20k typically sufficient, not affecting normal performance and efficiency. The coupling effect can be roughly estimated with the following equations, which assume a fixed linear input ramp and neglect the clamping effect of the body diode of the upper drive and the bootstrap capacitor. Other parasitic components such as lead inductances and PCB capacitances are also not taken into account. These equations are provided for guidance purpose only. Therefore, the actual coupling effect should be examined using a very high impedance (10M or greater) probe to ensure a safe design margin.
DS --------------------------------- dV ------ R C dV iss V GS_MILLER = ------- R C rss 1 - e dt dt -V
(EQ. 5)
R = R UGPH + R GI
C rss = C GD
C iss = C GD + C GS
VCC
BOOT CBOOT CGD DU
VIN D
ISL6597
UGATE RUGPH
G RGI CGS S
CDS
DL
QUPPER
PHASE
FIGURE 6. GATE TO SOURCE RESISTOR TO REDUCE UPPER MOSFET MILLER COUPLING
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FN9165.0 November 22, 2006
ISL6597 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.50 1.95 1.95 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.65 BSC 0.60 16 4 4 0.60 12 0.75 0.15 2.25 2.25 0.35 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 5 5/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN9165.0 November 22, 2006

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